AMD EPYC™ processors
Reliable security
Highest density inCPU
Consistent x86 ISA
Up to 128 "Zen4c" cores
Leadership in Cloud Performance
Today’s most powerful server processors
After the AMD Opteron series of server processors, a new series of server and HPC processors – AMD EPYC – has been launched. Its first series, called “Naples”, or the 7000 generation, was launched in 2017. This was followed by a series of improvements and significant innovations that have made EPYC processors the most powerful processors for the enterprise sector today.
The top of the range 9004 series models with Genoa/X and Bergamo can offer up to 128 cores. At the end of 2023, another separate family was added – the 8004 series processors with the “Siena” designation. These are tailored specifically for lower power consumption, have their own platform, designated SP6, and should complement the fourth-generation Epyc range with lower price tiers.
AMD EPYC™ 9004 Processors ("Genoa")
Compute
Up to 96 “Zen 4” x86 cores / 192 threads, 12 chiplets
1MB L2/core, 32MB L3/chiplet, up to 384MB L3 cache in total
Instruction set extended with BFLOAT16, VNNI, AVX512 (256bit datapath)
57bit/52bit memory addresses, virtual and physical
Updated IOD and new AMD Gen 3 Infinity Fabric
400W targeted TDP
Memory
12 DDR5 channels with ECC support @ 4800 MHz
Option of 2, 4, 6, 8, 10 or 12 channel interleaving
RDIMM, 3DS RDIMM
Up to 2 DIMM modules/channel with a total capacity of 6TB/CPU socket (256GB in case of RDIMM)
I/O
Up to 160 I/O lines (2P configuration) 5. PCIe generation, speeds up to 32Gb/s, divisible up to x1
12 bonus PCIe gen 3 lines in 2p configuration (8 lines/processor)
up to 32 IO lines for SATA
SDCI option
For 64 IO lines CXL 1.1 support with x4 divisibility
SP5 Platform
New socket, improved and increased power supply and regulation
Up to 4 AMD Infinity Fabric links with speeds up to 32Gb/s
Flexible connection topology
The Server Controller Hub p5es USB, UART, SPI, I2C and sub-packages.
Security
Dedicated security subsystem at the hardware level
Root-of-Trust hardware technology
AMD EPYC™ 9004 processor parameters
| Model | Number of cores | Number of threads | Base Frequency (GHz) | Max boost frequency | All core boost frekvency | TDP | L3 cache | Setting |
| 9654/P | 96 | 192 | 2.4 GHz | 3.7 GHz | 3.55 GHz | 360 W | 384 MB | 2P / 1P |
| 9634 | 84 | 168 | 2.25 GHz | 3.7 GHz | 3.10 GHz | 290 W | 384 MB | 2P / 1P |
| 9554/P | 64 | 128 | 3.10 GHz | 3.75 GHz | 3.75 GHz | 360 W | 256 MB | 2P / 1P |
| 9534 | 64 | 128 | 2.45 GHz | 3.7 GHz | 3.55 GHz | 280 W | 256 MB | 2P / 1P |
| 9454/P | 48 | 96 | 2.75 GHz | 3.8 GHz | 3.65 GHz | 290 W | 256 MB | 2P / 1P |
| 9354/P | 32 | 64 | 3.25 GHz | 3.8 GHz | 3.75 GHz | 280 W | 256 MB | 2P / 1P |
| 9334 | 32 | 64 | 2.7 GHz | 3.9 GHz | 3.85 GHz | 210 W | 128 MB | 2P / 1P |
| 9254 | 24 | 48 | 2.9 GHz | 4.15 GHz | 3.9 GHz | 200 W | 128 MB | 2P / 1P |
| 9224 | 24 | 48 | 2.5 GHz | 3.7 GHz | 3.65 GHz | 200 W | 64 MB | 2P / 1P |
| 9124 | 16 | 32 | 3 GHz | 3.7 GHz | 3.6 GHz | 200 W | 64 MB | 2P / 1P |
High frequency models
| Model | Number of cores | Number of threads | Base Frequency (GHz) | Max boost frequency | All core boost frekvency | TDP | L3 cache | Setting |
| 9474F | 48 | 96 | 3.6 GHz | 4.1 GHz | 3.95 GHz | 360 W | 256 MB | 2P / 1P |
| 9374F | 32 | 64 | 3.85 GHz | 4.3 GHz | 4.1 GHz | 320 W | 256 MB | 2P / 1P |
| 9274F | 24 | 48 | 4.05 GHz | 4.3 GHz | 4.1 GHz | 320 W | 256 MB | 2P / 1P |
| 9174F | 16 | 32 | 4.1 GHz | 4.4 GHz | 4.15 GHz | 320 W | 256 MB | 2P / 1P |
AMD EPYC™ with AMD 3D V-Cache™ technology ("Genoa-X")
The primary difference between the Genoa and Genoa-X processors is the use of so-called. 3D V-Cache technology, which is the principle of stacking L3 memory circuits in height, i.e. 3. size, which allows to achieve a significantly higher capacity of L3 cache without the need to dedicate a separate chiplet for it, which would increase both production costs and latency and transfer rate of such memory. The Genoa-X series processors boast up to 1.1GB of fast L3 cache.
AMD EPYC™ Gen 4 processors with AMD 3D V-Cache technology
| Model | # Jader | # Fibre | Default TDP | cTDP range | Fbase / Fboost | L3 Cache | DDR5 channels | PCIe Link |
|---|---|---|---|---|---|---|---|---|
| 9684X | 96 | 192 | 400 W | 320-400 W | 2.55GHz/3.7GHz | 1152 MB | 12 | x128 |
| 9384X | 32 | 64 | 320 W | 320-400 W | 3.1GHz/3.9GHz | 768 MB | 12 | x128 |
| 9184X | 16 | 32 | 320 W | 320-400 W | 3.55GHz/4.2GHz | 768 | 12 | x128 |
AMD EPYC™ 97X4 ("Bergamo")
Compute
Up to 128 “Zen4c” cores / 256 threads, 8 chiplets
1MB L2 per core, 2×16MB L3 CCX per chiplet
Instruction set extended with BFLOAT16, VNNI, AVX512 (256 bit line)
52bit / 57bit memory addresses in virtual and physical mode
TDP up to 400W (cTDP)
improved RAS
Memory
12 DDR5 channels with ECC support up to 4800MHz
Option of 2, 4, 6, 8, 10 or 12 channel interlacing
RDIMM, 3DS RDIMM
Up to 2 DIMM modules/channel with a total capacity of 6TB/CPU socket (256GB in case of RDIMM)
I/O
Up to 160 I/O lines (2P configuration) 5. PCIe generation, speeds up to 32Gb/s, divisible up to x1
12 bonus PCIe gen 3 lines in 2p configuration (8 lines/processor)
up to 32 IO lines for SATA
SDCI option
For 64 IO lines CXL 1.1 support with x4 divisibility
SP5 Platform
New socket, improved and increased power supply and regulation
Up to 4 AMD Infinity Fabric links with speeds up to 32Gb/s
Flexible connection topology
The Server Controller Hub p5es USB, UART, SPI, I2C and sub-packages.
Security
Dedicated security subsystem at hardware level
Root-of-Trust hardware technology
| Model | # Jader | # Fibre | Base F / Turbo F | L3 Cache | TDP |
|---|---|---|---|---|---|
| AMD EPYC™ 9754 | 128 | 256 | 2.25GHz / 3.1GHz | 256MB | 360W |
| AMD EPYC™ 9734 | 112 | 224 | 2.25GHz / 3.1GHz | 256MB | 360W |
AMD EPYC™ 8004 CPUs (“Siena”)
Compute
up to 64 cores and 128 threads
up to 128 MB total L3 cache
based on 5nm chipset with Zen 4c cores (16 cores in two CCX blocks per chipset)
base TDP 80-200 W
SP6 platform
separate platform, purely single-processor, no 2S servers
Six-channel memory controller with DDR5-4800 support (including ECC)
maximum RAM capacity 1,152 TB
support for RDIMM base modules
Connectivity
Provides 96 PCI Express 5.0 lanes
48 lines of which can be used as a coherent CXL 1.1 interface.
Models
AMD has prepared a total of 12 models for customers – six basic P models (with configurable TDP) for mainstream servers and six models of the PN series (fixed TDP) designed probably mainly for telecommunications or storage applications close to the embedded sector. There are six models in both series – one of each number of cores offered – configurations of 64, 48, 32, 24, 16 and 8 cores (always with SMT, i.e. double the number of threads).
New ZEN 4 Architecture
The new EPYC™ processor core is based on the ZEN 4 architecture with a 5nm manufacturing process, which significantly improves both the efficiency and performance of individual chips, but also brings improved cache and more powerful IO die. Thanks to these factors, AMD EPYC™ processors achieve 4. generation of much higher IPC values and high performance per core.
The latest 8004 series uses AMD’s Zen 4c core, which is implemented differently than Zen 4. Overall, the Zen 4c cores are a smaller and denser version of the Zen 4 cores, but retain the same functionality and performance characteristics.
Extended Instruction Set
For AMD EPYC™ 4 server processors. generation, several important new instruction elements and protocols have been added.
The main advantage is the presence of the AVX-512 instruction set, which significantly increases performance. The performance increase is most noticeable in HPC applications, as the processor is capable of handling twice as much data, making the AVX-512 a key feature for training AI models, for example. In addition, the BFloat16 instruction sets, VNNI and the CXL 1.1 protocol have been added, which enables high-speed interconnections between system peripherals.
A new type of operating memory
The new DDR5 operating memory standard with a maximum frequency of up to 4800 MHz is designed for the EPYC™ 9004 series processors. We have 12 memory lines per socket, which allows us to reach a capacity of up to 6 TB of RAM per processor.
The overall RAS factor of the processor (reliability, availability and serviceability) has also been improved, as memory errors can be a common reason for system crashes. Of course, ECC memory support also helps us prevent this.
PCI Express 5. generation
The new PCI-Express gen 5 data bus specification doubles the speed of the previous generation, bringing us to transfer speeds of up to 32 GT/s or 64 GB/s.
Infinity Fabric 3. generation
Infinity fabric 3. generation is based on an improved xGMI3 architecture that increases data throughput and improves latency.. This results in much better chip-to-chip communication, which benefits, for example, HPC systems.
AMD Infinity Guard
The 9004 Series EPYC™ processors feature AMD Infinity Guard technology, a layered security system integrated directly into the processor. It then runs right alongside your programs and data, which it can check in real time.
We have prepared a detailed comparison of current processor architectures — Intel Xeon, AMD EPYC™, IBM POWER, or ARM. In the article you will find tables with the parameters of each processor and also the advantages of their deployment for a specific type of applications.
Comparison of parameters with previous generations
Testing
We have test kits available to test the performance and features of AMD processors. If you are interested in testing, please fill out this form or contact Lukáš Vach.
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